Low Latency DRAM

GSI's Low Latency DRAMs (LLDRAMs) are high capacity, low latency memories. They provide significantly lower Random Cycle Time (tRC) and shorter burst DDR data transfers than commodity DRAM—which means higher transaction rates and more efficient bandwidth usage for the user. Additionally, their SRAM-like interface simplifies memory controller design. They are suitable for a variety of tasks, such as lookup tables and queue buffers in high speed networks, image processing, and any other applications where the random transaction rate requirement is greater than what commodity DRAM can provide, and the capacity requirement is greater than what SRAM can provide.

Low Latency DRAM II Series GSI's Low Latency DRAM (LLDRAM) is an ideal solution for advanced data networking applications. Its low Random Cycle Time (tRC), eight-bank memory array architecture, and double data rate transfers enable a level of performance unmatched by commodity DRAM. And its SRAM-like address interface makes it much easier to use. The result is a device that can maintain near-100% bus utilization for many networking tasks. GSI’s newest Low Latency DRAM family, the LLDRAM III, also offers higher density, lower power, and a lower pin count compared to competing solutions, and the wider data bus (x20 and x40) available in the HSTL versions enables the use of data encoding schemes (e.g., 8b/10b) and ECC protection options (e.g., protecting 32-bit data quantums using 6 or 7 ECC parity bits) that are impractical in traditional x18 and x36 RAMs. GSI's LLDRAM devices are ideal for 10GbE, 40GbE and 100GbE packet buffering and inspection tasks. They are the technology of choice on a variety of Network Processor Units and FPGA Architectures.

Low latency DRAM Series III GSI's Low Latency DRAM (LLDRAM) is an ideal solution for advanced data networking applications. Its low Random Cycle Time (tRC), eight-bank memory array architecture, and double data rate transfers enable a level of performance unmatched by commodity DRAM. And its SRAM-like address interface makes it much easier to use. The result is a device that can maintain near-100% bus utilization for many networking tasks. GSI’s newest Low Latency DRAM family, the LLDRAM III, also offers higher density, lower power, and a lower pin count compared to competing solutions, and the wider data bus (x20 and x40) available in the HSTL versions enables the use of data encoding schemes (e.g., 8b/10b) and ECC protection options (e.g., protecting 32-bit data quantums using 6 or 7 ECC parity bits) that are impractical in traditional x18 and x36 RAMs. GSI's LLDRAM devices are ideal for 10GbE, 40GbE and 100GbE packet buffering and inspection tasks. They are the technology of choice on a variety of Network Processor Units and FPGA Architectures.